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CDNLive Europe 2021 - Event Summary
October 19 - 20, 2021
On-Line
CICD 2021 - Event Summary
November 01 - 03, 2021
Guangzhou, China
Presentation Schedule
Don’t miss Tower's presentations:
Nov. 3rd, 2021 Wednesday
Venue: Huangpu Ballroom B, 1F, NARADA Hotel, Guangzhou
Time: 10:30-10:55
Sensing the World - Advanced CMOS Image Sensor Technology for 3D Imaging and Beyond
Speaker: Lei Qin, Vice President of China Operations, Tower Semiconductor Ltd.
ICCAD China 2022
December 26 - 27, 2022
Xiamen International Conference & Exhibition Center
Booth: #311, 320
Presentation Schedule
Don’t miss Tower's presentations:
Date: Dec 26, 2022
Time:15:55-16:15
Venue: Xiamen International Conference & Exhibition Center, 1st Floor, C4
Tower Semiconductor – Where Analog and Value Meet
Speaker: Lei Qin, VP of China Operations, Tower Semiconductor Ltd.
Date: Dec 27, 2022
Time: 08:40-09:00
Venue: Xiamen International Conference & Exhibition Center
Advanced 300mm 65nm BCD Power Management Platform – Best-in-class Technology Solutions Addressing the Extensive Power Market Needs
Speaker: Min Wang, Sales & FAE Manager, Tower Semiconductor Ltd.
2021 Annual Technical Global Symposium (TGS) – Europe / APAC Session - Event Summary
November 17, 2021
Online - Europe/APAC Session
9am Paris | 5pm Japan | 10am Israel
SPIフォーラム - Event Summary
November 04, 2020
On-Line - Zoom Webinar
Presentation information
Don’t miss Tower's presentations:
Time: 14:55-15:30 - Zoom
幅広いプロセスニーズに応える日本発のリーディング・アナログファンドリー
Name of speaker: 立岩 健二氏
Title: タワーパートナーズセミコンダクター株式会社(TPSCo)、プロセステクノロジーセンター開発戦略部 部長

http://www.semiconportal.com/spiforum/201104/
The Sensors Show 2020 Virtual - Event Summary
July 22 - 23, 2020
Online event
Presentation Schedule
Don’t miss Tower Semiconductor ONLINE presentation:
July 23, 2020 - Online
TRACK B - Industry 4.0, Manufacturing & IoT
EDT - 18:10
CEST/PDT - 15:10
IoT Sensors for The Industrial and Harsh Environments
AJ ElJallad - Senior Sales Director, Tower Semiconductor
Presentation Schedule
Don’t miss TowerJazz presentations:
Thursday, 4:30 PM BST on Thursday 11 June
Live Q&A following the session
Automotive Radar: Technologies and Tradeoffs
Presentor: Dr. Amol Kalburge
Power Management Technical Webinar - Event Summary
April 21, 2020
16:00 pm Israel / 14:00 pm UK / 9 am NY / 15:00 pm CET
Free Online Webinar:
Leading Power Management Technology Addressing Market Trends and Requirements for Extended Power and High Voltage Applications
Japan SOI Symposium 2019 - Event Summary
October 30 - 31, 2019
Yokohama @ Landmark Tower, 25F
Yubinbango220-8125, Yokohama, Kanagawa Prefecture Minato Mirai, Nishi 2-chome No. 2 No. 1 2
TowerJazz Presentation
Don’t miss TowerJazz presentations:
Oct. 31, 2019 | 11:55 - 12:20
Worlds first open commercial silicon photonics process and PDK from TowerJazz
Masanobu Kumazaki
Siemens U2U USA 2022 - Event Summary
May 03 - 04, 2022
Santa Clara, CA
USA
Presentation Schedule
Don’t miss Tower's presentations: https://event.sw.siemens.com/user2user-northamerica
Tue May 03, 2:45 PM - 3:15 PM PDT
mPower Power Integrity Enablement for High-speed SiGe BiCMOS technologies
The demand for SiGe foundry technology has grown with the rapid growth of popular wireline and wireless applications such as Optical networking, 5G, WiFi, GPS, IoT and Bluetooth. One of the key benefits of SiGe HBTs over CMOS is the ability to operate at higher power and frequencies, necessitating careful and comprehensive characterization and modeling of the Safe Operating Area (SOA) of the Integrated Circuit (IC) while ensuring the most optimized design. A key component of this goal relates to optimizing the design for performance and reliability of the interconnect. In this paper we’ll present a methodology to comprehensively implement and test the mPower Analog Integrity solution for Tower Semiconductor’s SBC18 platform. A reference flow will be presented to highlight the correct and efficient use of the tool for EM/IR signoff by product teams.

Samir Chaudhry - Director, Design Enablement, Tower Semiconductor
Masanobu Kumazaki - Tower Semiconductor
Dr. Joseph Davis - Sr. Director of Product Management, Siemens EDA
Image Sensors Europe 2021 - Event Summary
May 10 - 11, 2022
Park Plaza Hotel Victoria
London, UK
Presentation Schedule
Don’t miss Tower's presentations:
May 10, 2022
Time: 10am
Foundry perspectives - manufacturing and technology trends
Dr. Amos Fenigstein | Senior Director of CIS Research & Development
PCIM 2022 - Event Summary
May 10 - 12, 2022
Nürnberg
Booth: #6-431
Siemens U2U Europe 2022 - Event Summary
May 12, 2022
Munich, Germany
Presentation Schedule
Don’t miss Tower's presentations: https://event.sw.siemens.com/user2user-europe/agenda
May 12 - Ballroom Munich I + II, IC Backend Track 1
2:15 PM - 2:45 PM GMT
mPower Power Integrity Enablement for High-speed SiGe BiCMOS technologies
The demand for SiGe foundry technology has grown with the rapid growth of popular wireline and wireless applications such as Optical networking, 5G, WiFi, GPS, IoT and Bluetooth. One of the key benefits of SiGe HBTs over CMOS is the ability to operate at higher power and frequencies, necessitating careful and comprehensive characterization and modeling of the Safe Operating Area (SOA) of the Integrated Circuit (IC) while ensuring the most optimized design. A key component of this goal relates to optimizing the design for performance and reliability of the interconnect.

In this paper we’ll present a methodology to comprehensively implement and test the mPower Analog Integrity solution for Tower Semiconductor’s SBC18 platform. A reference flow will be presented to highlight the correct and efficient use of the tool for EM/IR signoff by product teams.

Ofer Tamir
Managing Director, Design Enablement, CAD and Design support
Tower Semiconductor
User2User Europe - Event Summary
November 04, 2019
Hilton Munich Airport
Terminalstreet Mitte 20
Munich
TowerJazz Presentation
Don’t miss TowerJazz presentations:
November 4th, 2019
Track: IC Design (Physical Implementation and Verification)
Time: 14:00-14:30
Implementation of a Transistor-Level DSPF Extraction Flow for Power Integrity Analysis
By: Ronen Hasnes
CDNLive SV 2022 - Event Summary
June 08 - 09, 2022
Santa Clara Convention Center
Booth: #S6
Presentation Schedule
Don’t miss Tower's presentations:
June 8th, 2022
Category: SYSTEM DESIGN AND ANALYSIS
Celsius Thermal Solver for Transistor-Level Thermal Analysis
David Quon - Design Support Engineer
Tower Semiconductor
OFC 2023
March 07 - 09, 2023
San Diego Convention Center, California, USA
Booth: #5317
APEC 2023
March 19 - 23, 2023
Orange County Convention Center
Orlando, FL, USA
Booth: #132
SNUG SV 2022 - Event Summary
March 30 - 31, 2022
Online - Presentation
Wednesday, March 30th
By Samir Chaudhry
Presentation Schedule
Don’t miss Tower's presentations: https://www.snug2022.com/en/agenda-page
Wednesday, Mach 30th
Time: 11:15 AM Pacific
Advances in Silicon Photonics Design Enablement with Synopsys Tools
Applications such as datacom, sensing, autonomous driving, and computing are driving demand for silicon photonics technology. For such Photonic Integrated Circuit (PIC) designs, both layout synthesis and physical verification demand innovative solutions to address unique challenges. For simulation and layout synthesis the Process Design Kit (PDK) should include accurate modeling of the active and passive devices as well as rapid synthesis capabilities so PIC designers can rapidly iterate to an optimum design. Once the layout is synthesized such non-traditional structures as “Curved lines / edges”, “Free angled edges” and “Acute angle corners” result in many false errors with traditional Design Rule Checking (DRC), and debug becomes difficult. On the other hand, there is concern about missing real errors with simplified screening algorithms. Additionally, optical devices provide a unique challenge for Layout Versus Schematic (LVS) verification related to wave-guide shapes and co-existence of electrical and optical pins. In this talk, we’ll present how these challenges are being addressed in an open foundry OptoCompiler PDK for design and simulation and the IC Validator platform for DRC and LVS, and are enabling PICs for a wide variety of applications.
SNUG Israel 2022 - Event Summary
September 20, 2022
Presentation - Only
Presentation Schedule
Don’t miss Tower's presentation: https://www.snug2022.com/en/agenda-page
September 20th
Room: Typhoon
Track: AMS & Physical Verification
Time: 15:30-16:00
Advances in Silicon Photonics Design Enablement with Synopsys Tools
Speaker: Ofer Tamir - Director Design Enablement
Tower Semiconductor

https://synopsys.cventevents.com/event/48327162-4c7a-4e73-bf36-c08c1a607724/websitePage:1d80d249-e24e-4581-bcca-43e24deda8c1?RefId=AEM%20Page
SPIE 2023
May 02 - 04, 2023
Orlando, FL, USA
Booth: #725
IMS 2023
June 11 - 16, 2023
San Diego, CA, USA
Booth: #826
タワージャズ協賛 SPIフォーラム 「自動運転の眼となるセンサ技術」 - Event Summary
August 28, 2019
Time: 13:30 - 17:00
Place:機械振興会館 地下3階 2号室
Address: 〒105-0011 東京都港区芝公園3-5-8
SOI Consortium China - Event Summary
September 16 - 17, 2019
Pudong Shangri-La Hotel
Shanghai, China
Presentation Schedule
Don’t miss TowerJazz presentations:
11:20-12:00

Session 1 - Deployment
Panel Discussion: 5G Deployment in China
TowerJazz Dr. Paul Hurwitz will be taking part of the panel
15:30-15:45

Session 3 - RF Value Chain
Specialized RFSOI foundry technology solutions to support rapid new product development
By Dr. Paul Hurwitz
TowerJazz & Synopsys Webinar: Foundry Silicon Photonics Process - Event Summary
July 16, 2019
Join us at one of those hours:
10 am CET (For EU and Asia audiences)
10 am PDT (For U.S. audience)

One hour is planned for this webinar, including Q&A sessions.
TGS USA 2019 - Event Summary
November 20, 2019
Hyatt Regency Santa Clara
5101 Great America Pkwy, Santa Clara, CA 95054
TGS Japan 2019 - Event Summary
September 19, 2019
INTERCONTINENTAL Tokyo Bay
1-16-2 Kaigan Minato-Ku Tokyo 105-8576 JAPAN

ホテル インターコンチネンタル 東京ベイ
〒105-8576 東京都港区海岸1丁目16番2号
TGS China - Event Summary
September 03, 2019
Parkyard Hotel Shanghai
上海博雅酒店
上海浦东新区碧波路699号
ECOC 2022 - Event Summary
September 18 - 22, 2022
Messe Basel
Switzerland
Booth: #377
Presentation Schedule
Don’t miss Tower's presentation:
18.09.2022
09:00 – 12:30
Room: Shanghai
Challenges and Advantages of III-V Integration in a Foundry Environment
Part of the 'Heterogeneous photonic integrated circuits' workshop

By Dr. Oleg Martynov, SiPho Process Development Manager

Session 1: Technologies, speaker #3

For additional details, visit here: https://www.ecoc2022.org/programme/workshops/10-programme-description/63-workshop-heterogeneous-pics
Autosens 2020 - Event Summary
November 17 - 19, 2020
On-Line
Detroit, USA
Presentation Schedule
Don’t miss Tower Semiconductor presentations:
Tuesday, November 17th, 2020
Emerging Role of Foundries in Bringing High Value Analog Products to Market
6:00pm - 6:30pm Detroit
Online - https://2020.auto-sens.com/agenda/session/334233
Presentation Schedule
Don’t miss Tower Semiconductor presentation:
On-Demand - GROW
Enabling Tower’s Leading-Edge BCD and RF Technologies with Siemens EDA Design Tools
Samir Chaudhry - Director, Design Enablement
Ofer Tamir - Senior Director Design Enablement
John Stabenow - Siemens Industries Software

https://events.sw.siemens.com/en-US/realizelive/agenda?agendaPath=session/542767

CadenceLIVE Americas 2021 - Event Summary
June 08 - 09, 2021
Digital Event
Presentation Schedule
Don’t miss Tower Semiconductor presentation:
Wednesday, June 9th
10:50 - 11:20
5G / RF
Silicon-Validated RFIC Package Co-Design Using Virtuoso RF Solution in Tower Semiconductor's CS18 RF SOI Technology
Abstract: Established and emerging wireless and wireline applications such as 5G, WiFi and 400-800G optical networking are driving the demand for highly optimized RFIC solutions. Typical RF/mmWave design flows rely on the use of multiple EDA tools often sourced from multiple EDA vendors. This is inherently inefficient and often error prone leading to delays in getting a product to market. In addition, there exist multiple combinations of design tools and flows that prevent a foundry from providing a golden reference flow that can be used by a large portions of the design community. In this paper we present a silicon validated unified RFIC design flow using the Virtuoso RF. The design flow is based on a high-power SP4T switch design in Tower Semiconductor’s CS18QT9x1 foundry technology. RF SOI switch designs offer a useful test-case for the Virtuoso RF design flow as they require co-design and co-optimization of both the silicon and the package which is a key strength of this design flow. The design flow will be used to present a consistent modeling and simulation methodology. A seamless hand-off between PDK provided model, metal interconnect extraction within the p-cell, metal interconnect modeling outside the p-cell using EMX and Clarity, and the flip-chip package will be presented, while maintaining a single unified database that is used for tape-out. Silicon validation of key small and large-signal metrics will be presented highlighting the importance of the tight interaction between foundry Virtuoso PDK and package modeling using EMX and Clarity.

https://events.cadence.com/event/70560da2-887d-4795-a8bc-1dcad2d95ca6/websitePage:a4c8ddce-9c7a-43e1-a4f8-2333a8e328a2
Tuesday, June 8th
12:00 - 12:30
Silicon Photonics
Streamlined Foundry-Compatible Custom Photonic IC Design with Ansys-Lumerical, Cadence Virtuoso Environment and Tower Semiconductor's Foundry PDK
Abstract: The demand for silicon photonics technology is growing with popular applications such as datacom (5G), artificial intelligence (AI), sensing, quantum computing and autonomous driving due to the improved bandwidth, sensing capabilities and reduced power consumption of photonic devices. For a typical photonic integrated circuits (PICs) design, designers use a combination of silicon validated components from a process design kit (PDK) and custom components that adhere to the foundry process design rules. However, as component layout designs and simulations are typically performed using different design tools and platforms, it is challenging to maintain the components’ compliance with the foundry process, while creating accurate compact models for efficient simulations. With a goal to reduce the design cycle time of custom photonic components for PICs designs, this work demonstrates a design workflow that facilitates photonic component layout, device simulation, compact model generation, and circuit simulation. This workflow leverages design tools from Cadence and Ansys-Lumerical, and a foundry silicon photonics PDK (PH18) from Tower Semiconductor. In this workflow, physical layout is the initial step of a custom photonic component design, where the curvilinear/polygon-based component shapes are drawn in Cadence Virtuoso Layout Suite by using the PH18 PDK. To assist device simulations on a custom design, the PDK provides a process file that contains all the information necessary for Lumerical DEVICE Suite to directly generate a 3D model from the design layout and to simulate it accurately for the foundry process. The device simulation results can then be used by the Lumerical CML Compiler to automatically build high-quality optical compact models in both the Lumerical INTERCONNECT and Verilog-A formats for different stages of the PIC design flow.

https://events.cadence.com/event/70560da2-887d-4795-a8bc-1dcad2d95ca6/websitePage:a4c8ddce-9c7a-43e1-a4f8-2333a8e328a2
DesignCon 2019 - Event Summary
January 29 - 31, 2019
Santa Clara Convention Center
Santa Clara, CA
Presentation Schedule
Don’t miss TowerJazz presentations:
January 29, 2019 / Ballroom - B
9AM - 12PM
Hand-on Tutorial - Lowering the Barrier to Entry for Electronic/Photonic ICs
Samir Chaudhry - Director, Design Enablement, TowerJazz
January 29, 2019 / Ballroom - B
4:45PM - 6PM
Panel Discussion - Photonics Coming of Age: The Emergence of PDKs
Samir Chaudhry - Director, Design Enablement, TowerJazz
ChipEx - Event Summary
May 13, 2019
Tel Aviv Convention Center
Rokach Boulevard 101, Tel Aviv - Yafo
Presentation Schedule
May 13, 2019
Tel Aviv, Israel
SESSIONS-ROUND 1
Track D - 12:40pm-1:00pm
Automotive Market Driven Solution - the Foundry Methodology to Mass Production
Dr. Eitan Shauly, Director of Integration, TowerJazz
APEC - Event Summary
March 17 - 21, 2019
Anaheim Convention Center
Anaheim, CA
Booth: #328
Presentation Schedule
Don’t miss TowerJazz presentations:
March 19, 2019 / Room 213B
08:30AM - 11:55 AM
Market Research: 65nm for Power Management IC - Sub 90nm PM Market Trends and Technology Advantages
Erez Sarig - Director of BD & Marketing PM/MS BU
SURGE Herzliya - Event Summary
November 28, 2018
Dan Accadia Herzliya Hotel,
Herzliya, Israel
User2User Europe - Event Summary
November 26, 2018
Park Hilton,
Munich, Germany
ICCAD 2018 - Event Summary
November 29 - 30, 2018
Zhuhai International Convention & Exhibition Center
Zhuhai, China
Booth: #112\113
Presentation
Don’t miss TowerJazz presentations:
November 30
11:00-11:20
"Analog Products in 65nm"
Qin Lei
Advanced Photonics IC Design Webinar - Event Summary
October 18, 2018
US/Pacific: 9:00AM
Asia/China: 4:00PM
EU/London: 9:00AM
Mentor and TowerJazz Automotive Workshop - Event Summary
November 21, 2019
Mentor, A Siemens Business
46871 Bayside Parkway
Fremont, CA
USA 94538
IS Americas - Event Summary
October 11 - 12, 2018
Hyatt Centric Fisherman's Wharf
San Francisco, CA, USA
Presentation Schedule
Don’t miss TowerJazz presentation:
13:00-13:30 | October 12
Hyatt Centric Fisherman's Wharf
Dr. Amos Fenigstein
"Future Trends in Imaging Beyond the Mobile Market"