イベント・セミナー情報

Speaker: Lei Qin, Vice President of China Operations, Tower Semiconductor Ltd.

Speaker: Lei Qin, VP of China Operations, Tower Semiconductor Ltd.

Speaker: Min Wang, Sales & FAE Manager, Tower Semiconductor Ltd.

Name of speaker: 立岩　健二氏
Title: タワーパートナーズセミコンダクター株式会社(TPSCo)、プロセステクノロジーセンター開発戦略部　部長

http://www.semiconportal.com/spiforum/201104/

AJ ElJallad - Senior Sales Director, Tower Semiconductor

Presentor: Dr. Amol Kalburge

Masanobu Kumazaki

The demand for SiGe foundry technology has grown with the rapid growth of popular wireline and wireless applications such as Optical networking, 5G, WiFi, GPS, IoT and Bluetooth. One of the key benefits of SiGe HBTs over CMOS is the ability to operate at higher power and frequencies, necessitating careful and comprehensive characterization and modeling of the Safe Operating Area (SOA) of the Integrated Circuit (IC) while ensuring the most optimized design. A key component of this goal relates to optimizing the design for performance and reliability of the interconnect. In this paper we’ll present a methodology to comprehensively implement and test the mPower Analog Integrity solution for Tower Semiconductor’s SBC18 platform. A reference flow will be presented to highlight the correct and efficient use of the tool for EM/IR signoff by product teams.

Samir Chaudhry - Director, Design Enablement, Tower Semiconductor
Masanobu Kumazaki - Tower Semiconductor
Dr. Joseph Davis - Sr. Director of Product Management, Siemens EDA

The demand for SiGe foundry technology has grown with the rapid growth of popular wireline and wireless applications such as Optical networking, 5G, WiFi, GPS, IoT and Bluetooth. One of the key benefits of SiGe HBTs over CMOS is the ability to operate at higher power and frequencies, necessitating careful and comprehensive characterization and modeling of the Safe Operating Area (SOA) of the Integrated Circuit (IC) while ensuring the most optimized design. A key component of this goal relates to optimizing the design for performance and reliability of the interconnect.

In this paper we’ll present a methodology to comprehensively implement and test the mPower Analog Integrity solution for Tower Semiconductor’s SBC18 platform. A reference flow will be presented to highlight the correct and efficient use of the tool for EM/IR signoff by product teams.

Ofer Tamir
Managing Director, Design Enablement, CAD and Design support
Tower Semiconductor

By: Ronen Hasnes

David Quon - Design Support Engineer
Tower Semiconductor

The CMOS image sensor landscape keeps evolving to address new applications, in Industry 4.0, medical, automotive or consumer imaging. CMOS foundries must adapt to the various ideas and concepts Image Sensor suppliers in order to stay relevant. In this talk, we will discuss some of the solutions developed by Foundries to expand the use of imaging technology, with examples in the fields:
• Infrared Imaging
• Charge domain BSI Global shutter solutions
• Above IC technologies going beyond Imaging.

Benoit Dupont, Sensors and Display Marketing Director at Tower Semiconductor

 
For agenda and additional details - Click here >

Speaker: Ofer Tamir - Director Design Enablement
Tower Semiconductor

https://synopsys.cventevents.com/event/48327162-4c7a-4e73-bf36-c08c1a607724/websitePage:1d80d249-e24e-4581-bcca-43e24deda8c1?RefId=AEM%20Page

TowerJazz Dr. Paul Hurwitz will be taking part of the panel

By Dr. Paul Hurwitz

Part of the 'Heterogeneous photonic integrated circuits' workshop

By Dr. Oleg Martynov, SiPho Process Development Manager

Session 1: Technologies, speaker #3

For additional details, visit here: https://www.ecoc2022.org/programme/workshops/10-programme-description/63-workshop-heterogeneous-pics

6:00pm - 6:30pm Detroit
Online - https://2020.auto-sens.com/agenda/session/334233

Samir Chaudhry - Director, Design Enablement
Ofer Tamir - Senior Director Design Enablement
John Stabenow - Siemens Industries Software

https://events.sw.siemens.com/en-US/realizelive/agenda?agendaPath=session/542767

Abstract: Established and emerging wireless and wireline applications such as 5G, WiFi and 400-800G optical networking are driving the demand for highly optimized RFIC solutions. Typical RF/mmWave design flows rely on the use of multiple EDA tools often sourced from multiple EDA vendors. This is inherently inefficient and often error prone leading to delays in getting a product to market. In addition, there exist multiple combinations of design tools and flows that prevent a foundry from providing a golden reference flow that can be used by a large portions of the design community. In this paper we present a silicon validated unified RFIC design flow using the Virtuoso RF. The design flow is based on a high-power SP4T switch design in Tower Semiconductor’s CS18QT9x1 foundry technology. RF SOI switch designs offer a useful test-case for the Virtuoso RF design flow as they require co-design and co-optimization of both the silicon and the package which is a key strength of this design flow. The design flow will be used to present a consistent modeling and simulation methodology. A seamless hand-off between PDK provided model, metal interconnect extraction within the p-cell, metal interconnect modeling outside the p-cell using EMX and Clarity, and the flip-chip package will be presented, while maintaining a single unified database that is used for tape-out. Silicon validation of key small and large-signal metrics will be presented highlighting the importance of the tight interaction between foundry Virtuoso PDK and package modeling using EMX and Clarity.

https://events.cadence.com/event/70560da2-887d-4795-a8bc-1dcad2d95ca6/websitePage:a4c8ddce-9c7a-43e1-a4f8-2333a8e328a2

Abstract: The demand for silicon photonics technology is growing with popular applications such as datacom (5G), artificial intelligence (AI), sensing, quantum computing and autonomous driving due to the improved bandwidth, sensing capabilities and reduced power consumption of photonic devices. For a typical photonic integrated circuits (PICs) design, designers use a combination of silicon validated components from a process design kit (PDK) and custom components that adhere to the foundry process design rules. However, as component layout designs and simulations are typically performed using different design tools and platforms, it is challenging to maintain the components’ compliance with the foundry process, while creating accurate compact models for efficient simulations. With a goal to reduce the design cycle time of custom photonic components for PICs designs, this work demonstrates a design workflow that facilitates photonic component layout, device simulation, compact model generation, and circuit simulation. This workflow leverages design tools from Cadence and Ansys-Lumerical, and a foundry silicon photonics PDK (PH18) from Tower Semiconductor. In this workflow, physical layout is the initial step of a custom photonic component design, where the curvilinear/polygon-based component shapes are drawn in Cadence Virtuoso Layout Suite by using the PH18 PDK. To assist device simulations on a custom design, the PDK provides a process file that contains all the information necessary for Lumerical DEVICE Suite to directly generate a 3D model from the design layout and to simulate it accurately for the foundry process. The device simulation results can then be used by the Lumerical CML Compiler to automatically build high-quality optical compact models in both the Lumerical INTERCONNECT and Verilog-A formats for different stages of the PIC design flow.

https://events.cadence.com/event/70560da2-887d-4795-a8bc-1dcad2d95ca6/websitePage:a4c8ddce-9c7a-43e1-a4f8-2333a8e328a2

Samir Chaudhry - Director, Design Enablement, TowerJazz

Samir Chaudhry - Director, Design Enablement, TowerJazz

Dr. Eitan Shauly, Director of Integration, TowerJazz

Erez Sarig - Director of BD & Marketing PM/MS BU

Qin Lei

"Future Trends in Imaging Beyond the Mobile Market"